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ASIC design workshop 2018, K Ramakrishnan College of Engineering, Trichy, Tamil Nadu, 10th - 12th September 2018
View Event Website Poster Link Brochure Link
- Event Type:
- Venue/Offline Mode
- Start Date :
- 10th September 2018
- End Date :
- 12th September 2018
- Location :
- Trichy, Tamil Nadu
- Organizer :
- K Ramakrishnan College of Engineering
- Category :
- Workshop
About Event
Opportunities in VLSI Industries & Hardware modeling using Verilog HDL & hands- on training in CAD tools.
The workshop will cover the following topics:
Combinational circuits design.
Sequential circuits design.
Synchronous circuits design.
Memories design.
FSM design.
Hardware verificationusing latest FPGA device.
Testbenches.
Design for test.
Events
Workshops
Workshops
Opportunities in VLSI Industries & Hardware modeling using Verilog HDL & hands- on training in CAD tools.
Event Guests
Mr.ananthraj,
Sr.ASIC verification engineer,
R&D department,
Sandisk,
Bangalore.
Departments:
CSE ECE EEE BioMedical DesignAccommodation
100/- per day
How to reach K Ramakrishnan College of Engineering, Trichy
Trichy central-samayapuram toll plaza(chennai or velore bus)
or
chatram-samayapuram toll plaza(perambalur bus)
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